Performance enhancement and characterization techniques for GaN power devices

Abstract

GaN-on-Si power devices are highly desirable for energy-efficient and compact power conversion systems. However, their performance and stability/reliability can be adversely affected by dynamic charging/discharging of interface and bulk traps. These issues need to be addressed by developing new processing technologies or structure designs, while appropriate characterization techniques are essential to reveal the impacts of interface and bulk traps on device characteristics. In this work, we are going to present: (1) gate stack engineering techniques to enhance threshold voltage (VTH) stability of insulated-gate GaN transistors even at elevated junction temperature; (2) fast dynamic characterization techniques with minimized measurement delay (120 ns) to reveal the impact of VTH shift on ON-resistance (RON), which facilitates the evaluation on how much VTH shift a GaN power transistor can tolerate; (3) vertical leakage mechanisms that ultimately limit the breakdown voltage of GaN-on-Si power devices.