Abstract
In this paper, we describe the performance elements used in our 28nm bulk devices with the gate first high-k/metal gate scheme for high performance applications. By using the innovative stressor integrations including improved stress memory technique (SMT), optimized embedded SiGe process and dual stress liner, Ieff of ~540/360 uA/um have been obtained for NMOS and PMOS respectively with the gate length of 28nm and pitch of 113.4nm (Ioff =100 nA/um, Vdd=0.85V). Good Vth mis-match (Avt of ~2.4 mV-um) has been achieved for SRAM devices with the high-k/metal gate, signal-noise-ratio of ~0.2V has been demonstrated in the high performance SRAM cell (0.152 um <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) with Vdd of 0.85V.
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