Performance comparison of static CMOS and MCML gates in sub-threshold region of operation for 32nm CMOS technology

Abstract

This paper investigates the performance of static CMOS logic circuits and MOS current mode logic (MCML) circuits in sub-threshold region. The simulations are based on 32 nm Berkeley predictive technology model (BPTM) running in HSPICE software. It is found that MCML logic circuits exhibit a decrease in delay and so decrease in overall PDP, which is one of our performance measures, with scaling of input voltage which is contrary to the behavior of static CMOS logic circuits. The results show a propagation delay improvement of more than 10 times when using MCML logic over CMOS logic in sub-threshold region of operation. Further the performance in terms of PDP of MCML logic circuits is improved by a factor of 7-10 when the input voltage is scaled down from 0.4 V to 0.2 V. .The results of various circuit simulations have been illustrated and compared by defining certain performance measures and the trade off between these performance measures.