Performance Comparison of MCML, PFSCL, and Dynamic CML Gates with Parametric Analysis in 45 nm CMOS Technology

Abstract

In this survey, the comparison results of current mode logic styles such as MOS Current Mode Logic (MCML), Dynamic Current Mode Logic (DyCML), and Positive Feedback Source Coupled Logic (PFSCL) gate structures are analyzed. In this, MCML and PFSCL are static logic circuits. The dynamic logic uses a clock signal as one of the inputs. The simulation results are performed at a voltage of 1 V and a temperature of 27 °C. The values of power, propagation delay, and power delay product are obtained and analyzed using the Cadence Virtuoso tool. The power and the delay values are verified with Monte Carlo simulations using a histogram plot of 200 samples. The process variations for different corners are simulated and the parametric analysis with different temperatures are compared for the different topologies of current mode logic gates. From the comparison, it is clear that Dynamic CML provides high performance and operates in a low-power environment.