Abstract
In recent technologies, device scaling leads to increase in dynamic power, sub threshold leakage, and degradation of noise margins which are vital obstacles in future generation memory circuits. This paper explores the design of a 6T cell of SRAM. A low power, large SNM 6T cell using conventional MOSFET and DG MOSFET is designed and the results of simulation using ATLAS shows that a 6T cell using DG MOSFET gives better performance compared to conventional MOSFET in terms of SNM even at low supply voltages down to 0.3V.
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