Performance Bounds of ADC-Based Receivers Due to Clock Jitter

Abstract

The maximum tolerable clock jitter for high-speed ADCs is pessimistically predicted by Nyquist-rate input sinusoidal tests. We prove that the jitter can be greatly relaxed in the presence of lossy channels in wireline systems. We derive compact expressions that allow PLL designers to decide how much jitter can be tolerated for a given channel loss and symbol rate.