Performance Benchmarking of 32 nm Predictive Technology Model CMOS with Silicon Nanowire Physic-Based Compact Model of Field-Effect Transistors for Digital Logic Applications

Abstract

New variation of nanostructures are introduced and developed to sustain Moore's Law as device dimension is scaled drastically. Among those low dimensional technological innovation is silicon (Si) nanowire field-effect transistor (NWFET). The usefulness of Si NWFET is its compatibility with existing complementary metal-oxide semiconductor (CMOS) technology that been widely pursued for more than four decades. Device simulation of nanowire is essential to explore physics in depth and to assess, quantify and benchmark the device performance metrics with a nanoscale metal-oxide semiconductor field-effect transistor (MOSFET). SPICE model of Si NWFET is constructed based on the device model proposed by researchers from Purdue University. A semi-empirical solution of the self-consistent is presented so that the device model is made portable and can be simulated in SPICE and other platform. Then, silicon-based digital logic circuit namely inverter, NOR and NAND are simulated and analysed. The circuit performances of nanowire digital gates are then compared against 32 nm MOSFET in terms of energy-delay product, power-delay product, propagation delay and average power dissipation. The results shown that silicon nanowires perform better than 32 nm MOSFET generally due to the high velocity transport of quasi ballistic carriers and superior gate control.