Abstract
New variation of nanostructures are introduced and developed to sustain Moore's Law as device dimension is scaled drastically. Among those low dimensional technological innovation is silicon (Si) nanowire field-effect transistor (NWFET). The usefulness of Si NWFET is its compatibility with existing complementary metal-oxide semiconductor (CMOS) technology that been widely pursued for more than four decades. Device simulation of nanowire is essential to explore physics in depth and to assess, quantify and benchmark the device performance metrics with a nanoscale metal-oxide semiconductor field-effect transistor (MOSFET). SPICE model of Si NWFET is constructed based on the device model proposed by researchers from Purdue University. A semi-empirical solution of the self-consistent is presented so that the device model is made portable and can be simulated in SPICE and other platform. Then, silicon-based digital logic circuit namely inverter, NOR and NAND are simulated and analysed. The circuit performances of nanowire digital gates are then compared against 32 nm MOSFET in terms of energy-delay product, power-delay product, propagation delay and average power dissipation. The results shown that silicon nanowires perform better than 32 nm MOSFET generally due to the high velocity transport of quasi ballistic carriers and superior gate control.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.