Performance and Timing Yield Enhancement using Highway-on-Chip Planning

Abstract

Interconnect mis-prediction is a dominant problem in nanoscale design that may weaken the quality of physical design algorithms or may even increase the design divergence possibility. In this paper, a new interconnect planning technique is presented based highway-on-chip approach. In this methodology, some highways are planned on chip and the location and amount of resource in highways are gradually determined during the placement process. Experimental results show that by using this technique, performance of the attempted benchmarks is improved by 13.66% on average and timing yield of the attempted circuits is improved by 10.02% on average. It is also shown that the results of this technique become better when the size of circuits grows.