Performance and stability of amorphous InGaZnO thin film transistors with a designed device structure

Abstract

We propose a specifically designed structure to fabricate thin-film transistors using amorphous indium-gallium-zinc-oxide (a-IGZO) films as the active channel layers. The I-shaped gate electrode is employed to define the channel width, reducing overlaps between the gate and source/drain electrodes. The devices with such a structure exhibit acceptable electrical performance and stability after annealing treatment. The XPS data show that the as-deposited a-IGZO film has not a very dense structure that may induce shallow traps. A shallow trap model is proposed to explain the large threshold voltage shifts of the as-deposited device. Annealing treatment can eliminate these shallow traps and improve the device stability.