Performance and Robustness of 3-D Integrated SRAM Considering Tier-to-Tier Thermal and Supply Crosstalk

Abstract

This paper analyzes the effect of tier-to-tier thermal and supply crosstalk on the performance and robustness of the static random access memory (SRAM) within a 3-D stack under crosstalk influence of the logic cores. Our framework integrates distributed process variation aware circuit analysis, RC-based thermal simulation, and distributed RLC-based power delivery network simulation. The analysis shows when the logic cores and SRAMs are integrated in 3-D stack, the thermal and supply crosstalk degrade the SRAM performance and noise margin during read and write operations.