Performance and reliability enhancement of flexible low-temperature polycrystalline silicon thin-film transistors via activation-annealing temperature optimization

Abstract

The high performance and reliability of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) on flexible substrates need to be ensured for the proper operation of advanced flexible organic light-emitting diode (OLED) displays. However, due to the heat-sensitive components of flexible LTPS TFTs, their fabrication process faces challenges in the temperature management of its thermal treatment procedures such as activation annealing, which is an essential step in the in-line fabrication process of LTPS TFTs for activating dopants and reducing silicon lattice-related structural defects. In this work, we investigate the optimization of the activation-annealing process through the modulation of its process temperature. As the activation-annealing temperature was increased from 320 °C to 370 °C, the electrical characteristics and reliability of flexible LTPS TFTs improved owing to a decrease in the gate dielectric/channel interface and bulk channel defects. However, as the temperature was further increased to 420 °C, considerable degradations in device performance and reliability were observed due to a significant increase in the deep-level gate dielectric/channel interface and bulk channel defects. Physical analysis revealed that significant dehydrogenation, in which the breakage of Si−H bonds causes excess Si dangling bonds, occurred at 420 °C. This work shows that a fine temperature optimization of the activation annealing process is a necessary procedure for ensuring highly performant and reliable LTPS TFTs on flexible substrates.