Performance Analysis of Trench Power MOSFETs in High-Frequency Synchronous Buck Converter Applications

Yali Xiong,Xu Cheng,Xiangcheng Wang,Lina Guo,Pavan Kumar,Z John Shen

doi:10.1155/2008/412175

Abstract

This paper investigates the performance perspectives and theoretical limitations of trench power MOSFETs in synchronous rectifier buck converters operating in the MHz frequency range. Several trench MOSFET technologies are studied using a mixed-mode device/circuit modeling approach. Individual power loss contributions from the control and synchronous MOSFETs, and their dependence on switching frequency between 500 kHz and 5 MHz are discussed in detail. It is observed that the conduction loss contribution decreases from 40% to 4% while the switching loss contribution increases from 60% to 96% as the switching frequency increases from 500 KHz to 5 MHz. Beyond 1 MHz frequency there is no obvious benefit to increase the die size of either SyncFET or CtrlFET. The RDS(ON)×QG figure of merit (FOM) still correlates well to the overall converter efficiency in the MHz frequency range. The efficiency of the hard switching buck topology is limited to 80% at 2 MHz and 65% at 5 MHz even with the most advanced trench MOSFET technologies.

Highlights

Trench powerMOSFETsare widely used as both control and synchronous rectifier switches (CtrlFET and SyncFET) in buck converters for computer, telecommunication, and consumer applications [1,2,3,4,5]
We have comprehensively investigated the performance perspectives and theoretical limitations of trench power MOSFETs in synchronous rectifier buck converters over a wide range of operating conditions
Individual power loss contributions from the CtrlFETs and SyncFETs and their dependence on switching frequency between 500 kHz and 5 MHz are discussed in detail

Summary

Introduction

Trench powerMOSFETsare widely used as both control and synchronous rectifier switches (CtrlFET and SyncFET) in buck converters for computer, telecommunication, and consumer applications [1,2,3,4,5]. The analysis, modeling, and optimization of power MOSFET performance in synchronous buck converters have become the focus of a significant amount of research work in the past few years [8,9,10,11,12]. The objective is to identify the optimum design of the CtrlFETs and SyncFETs that offer the highest converter efficiency. The previous work addressed this goal with varied levels of success, but several issues still remain open especially in light of ever-evolving DC/DC converter design requirements

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Conclusion