Performance Analysis of Solid-State Fractional Capacitor-Based Analog $$\hbox {PI}^\lambda \hbox {D}^{\mu }$$ Controller

Abstract

This work reports analog implementation of $$\hbox {PI}^\lambda \hbox {D}^\mu $$ controller realized by solid-state fractional capacitor. The fractional integrator is implemented with a solid-state fractional capacitor fabricated by the authors, and the fractional differentiator circuit is implemented using optimal pole–zero interlacing algorithm. The paper proposes a tuning algorithm for finding the parameters of the fractional $$\hbox {PI}^{\lambda }\hbox {D}^{\mu }$$ controller to get the desired time domain performance. Using the tuning algorithm, the combinations of $$\lambda $$, $$\mu $$ and gain values of the controller are evaluated on a DC motor emulator to limit % overshoot $$\le $$ 12% and settling time < 13 ms. The performance of the controller (with $$\lambda = \mu = 0.4$$) on speed regulation of DC motor emulator has also been discussed in detail both in simulation and in hardware.