Abstract
ABSTRACTThe design and characteristics of an nMOS-shielded channel double-gate junctionless transistor (SC DG JLT) were compared with shielded channel double-gate (SC DG) transistor with equal dimensions using TCAD. It is found that SC DG JLT’s on-state current is maximum compared to SC DG transistor. SC DG JLT devices may be associated with both low drain-induced barrier lowering (DIBL) and off-state current than SC DG transistor device. SC DG JLT reduces the 30% effects of band-to-band tunnelling in sub-threshold region. Threshold voltage variation is minimum in SC DG JLT compared to SC DG transistor device. It has been found that SC DG JLT’s electric field at drain side is 60% lower compared to SC DG transistor, indicating minimum hot electron effect. In this paper, the important parameters such as transconductance Gm, drain conductance gd, transconductance generation efficiency Gm/Ids are focused using 2-D TCAD simulation. In sub-threshold region, SC DG JLT has maximum efficiency compared to SC DG transistor to convert DC power into AC frequency.
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