Abstract
The pertinent choice of D flip-flop is an indispensible cell in any logic cell library. The transitions in flip-flop dictates power consumption in sensor nodes. Power-Delay-Area are the Figures of Metric (FoM) which decides the choice of flip-flop used in wireless sensor nodes (WSN). In this paper, we identified PowerPC 603 flip-flop as the candidate suitable for WSN after conducting robust analysis of several flip-flop circuits proposed in literature. Subthreshold design is an effective technique for designing signal processing circuits needed in wireless sensor nodes powered by sources with limited energy. To set the tone in current context, we have simulated the performance of PowerPC603 flip-flop in subthreshold region using Nano scale CMOS devices below 16nm till 7nm using BSIM-CMG (a compact model for the class of common multi-gate FETs) and EKV model extracted from BSIM-CMG models. Simulations are carried out with HSPICE (Level=55) and the performance of PowerPC 603 flip-flop are analyzed for the two models. The minimum Power Delay Product (PDP) is 510 aJ and 18.35 aJ for 14nm technology in BSIM-CMG and EKV models respectively at 0.3V.
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