Performance analysis of Pocket Doped Junction-Less TFET

Abstract

The Junction less tunnel field-effect transistor (JLTFET) is a charming device because of its brilliant electrical properties and less inconstancy in contrast with MOSFET at the nanometer system. Right now, explore a silicon-based pocket doped JLTFET in which an InAs pocket is embedded over the source-channel intersection to upgrade tunneling likelihood. Right now, have thought about DC and linearity parameter analysis for the conventional and pocket doped JLTFET (PD-JLTFET) in terms of electric field, transfer characteristics, transconductance, second-order voltage intercept point, third-order voltage intercept point, third-order input intercept point and 1-dB compression point. Also, we have analyzed the impact of spacer length variation over the source-channel intersection. The proposed PD-JLTFET has indicated higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> proportion (~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> ) and improved subthreshold swing (~9.08 mV/decade). The remarkable qualities showed by PD-JLTFET make it a potential device for low power applications.