Performance analysis of parallel array of nanowires and a nanosheet in SG, DG and GAA FETs

Abstract

Multiple arrays of Si nanowires are required for high performance applications with high current drive requirements. Densely packed arrays are significantly affected by electrostatic screening effects deteriorating the DC and AC performance of the individual nanowire (NW). This study compares the impact of screening effects in single gate, double gate and gate all-around nanowire FETs with nanosheet FETs based on experimental data and calibrated TCAD simulation results. Moreover, evolving the NW array into nanosheet transistors turned out to yield superior performance and thus might be a candidate for future high performance electronics. We identified NW pitches of less than four times the NW diameter to be critical for the performance of an individual NW in the array with a NW performance degradation of up to 50%. However, the performance gain by having more NWs within the same area in a densely packed array overcompensates the performance drop of the individuals NWs in the array.