Abstract
In this study, we propose a low power, high efficient Low Density Parity-Check Code (LDPC) Decoder Architecture for error detection and correction applications. LDPC codes have been adopted in latest wireless standards such as satellite and mobile communications since they possess superior error-detecting and correcting capabilities. As technology scales, memory devices become larger and more powerful and low power consumption based error correction codes are needed. This study discuses the design and analysis of check node unit and variable node unit in LDPC decoder. The architecture is synthesized on Xilinx 9.2i and simulated using Modelsim, which is targeted to 90 nm device. Synthesis report shows that the proposed architecture reduces the hardware utilization and power consumption when compared to the conventional architecture design.
Highlights
There are several decoding algorithms conventionally used
The proposed work results shows that the system incorporated with Low Density Parity-Check Code (LDPC) leads to lower power consumption in terms of slices, Look Up Tables and Flip Flops
The parameters considered for investigation include number of Slices (S), number of Look Up Table (LUT’s), Slice Latches (SL), gate counts (GA), Power Consumption (PC) and Area Utilization
Summary
There are several decoding algorithms conventionally used. Out of these, the Belief Propagation (BP) algorithmLow Density Parity-Check (LDPC) codes are known to have excellent performance for high speed data attains an excellent decoding performance. There are several decoding algorithms conventionally used. Low Density Parity-Check (LDPC) codes are known to have excellent performance for high speed data attains an excellent decoding performance. For the standard BP algorithm, numerous multiplicative and transmission and low complexity. Moderatelength or short length binary LDPC codes have been logarithmic computations are necessary to compute the check node. The Min-Sum (MS) algorithm, interchanges shown to have an early error floor and degraded decoding performance. These codes have been implemented in various standards such as WiMax Even though performance is reduced, the hardware complexity of the BP algorithm is significantly minimized, by replacing
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