Performance Analysis of Gaussian Normal Basis GF ($2^{m}$) Serial Multipliers and Inverters

Abstract

Cryptography hardware processors enable fine-tuned designs supporting secure communications in extreme environments such as resource-constrained applications. Secure communications of resource-constrained wireless devices require efficient cryptographic arithmetic circuits such as finite field multipliers and inverters. Gaussian Normal Basis (GNB) provides cost-free squaring operation which is advantageous in repeated square-multiply cryptographic algorithms. In this paper, we realize the Itoh-Tsuji inverter based on the parallel-in-serial-out multiplier, for the first time to the best of our knowledge. We also report the design complexity of the GNB multipliers and inverters using the same technology and provide a comprehensive analysis of existing GNB multipliers and inverters in current literature. We conduct performance analysis of different multiplier architectures with varying digit sizes ( $d\geq 1$ ) and bit-serial ( $d=1$ ) inverter architectures. We also analyze the power variation of multiplier/inverter architectures for controlled input variations. The area, time complexities, and power analysis are reported using the standard 65nm CMOS and the open-source 45nm NangateOpenCellLibrary technology. The results show that the new inverter design has a competitive area and power consumptions compared to IT inverter based on Parallel-In-Parallel-Out multiplier when implemented using 65nm CMOS Standard cell library.