Performance Analysis of Full Adder based on Domino Logic Technique

Abstract

In modern VLSI area efficient devices are most used because most of the devices are becoming portable. The Domino logic technique is often employed in designing the area efficient and high-speed devices. In this research paper. one-bit full adder circuit using CMOS based logic and domino-based log icon Cadence Virtuoso 6.1.7 has been designed based on 0.18um technology having the supply voltage of 3V. This research paper is mainly centralized on the design of area efficient and fast speed devices. This work evaluates the performance CMOS and Domino logic based on full adder circuit in terms of delay and power consumption. It was found that Domino logic based one - bit full adder circuit occupied 28.57%lesser area and introduces 47.36% less delay as comparison to one -bit full adder circuit. based on CMOS logic.