Performance Analysis of FinFET-Based Static Random Access Memory Design

Abstract

The short-channel effect (SCE) limits the performance of planar MOSFET devices in conventional complementary metal oxide semiconductor (CMOS) technologies due to the ongoing scaling (SCE). FinFETs, Nanowire, and Nanosheet devices are examples of multi-gate FETs (MuG-FETs), which have emerged as the most promising method for extending CMOS scaling past sub-22 nm technology. One of the crucial parts of CPUs is SRAM. This paper provides a comparative analysis of various SRAM designs using CMOS and FinFET devices. The performance of SRAM design is evaluated using propagation delay, power dissipation, and power delay product (PDP).