Abstract
Automatic Test Pattern Generation (ATPG) is one of the best testing technique that has been used for decades. But it is very difficult to u se A TPG f or testing in the case of large and complex designs, such as SOC type of ICs. Of the many research techniques, the best chosen solution is Embedded Deterministic Test (EDT) which includes some additional logic structures to the design. EDT helps in a dramatic reduction in the test cost, due to the reduced test volume and reduced ATE memory usage. In this paper, analysis of Embedded Deterministic Test (EDT) structures on ISCAS-89 benchmark circuits by using Mentor graphics Tessent™ test CAD tool were done.
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