Performance analysis of clock-regulated queues with output multiplexing in three different 2 × 2 crossbar switch architectures

Abstract

Switches in interconnection networks for highly parallel shared memory computer systems may be implemented with different internal buffer structures. For a 2 × 2 synchronous switch, previous studies have often assumed a switch composed of two queues, one at each output, each of which has unbounded size and may accept two inputs every clock cycle. Hardware implementations may actually use simpler queue designs and will have bounded size. Two additional models for a 2 × 2 switch using queues that may accept only one input at a time are analyzed. The first uses four queues, one for each input/output pair. The second uses two queues, one at each input. In each case, a multiplexer blocks one queue if two queues desire the same output, making these models more difficult to analyze than the previous model. Maximum bandwidth, expected queue length, expected waiting time, and queue length distribution are presented for both models, with unbounded queue size and with queue size equal to 1.