Performance Analysis of Cache Coherence Protocols for Multi-core Architectures

Abstract

Shared memory multi-core processors are becoming dominant in todays computer architectures. Caching of shared data may produce a problem of replication in multiple caches. Replication provides reduction in contention for shared data items along with reduction in access latency and memory bandwidth. Caching of shared data that are being read by multiple processors simultaneously, introduces the problem of cache coherence. There are two different techniques to track the sharing status viz. Directory and Snooping. This work gives an emphasis on the study and analysis of impact of various system parameters on the performance of the basic techniques. The performance analysis of this work is based on the number of processors, available bandwidth and cache size. The prime aim of this work is to identify appropriate cache coherence protocol for various configurations. Simulation results have shown that snooping based systems are appropriate for high bandwidth systems and is the ideal choice for CPU and communication intensive workloads while directory based cache coherence protocols are suitable for lower bandwidth systems and will be more appropriate for memory intensive workloads.