Performance analysis of a novel hetero-junction tunnel FET based SRAM at 0.3V supply voltage

Abstract

In this paper, the stability/performance of the conventional SRAM cell architectures have been demonstrated using a novel hetero-junction double gate tunnel FET (H-DGTFET) device at 15 nm technology node. This device has improved ON-current (I ON ) because of the decrease in width of the depletion region due to a highly doped layer placed in the channel near the source-channel junction. It results in an improved I ON /I OFF ratio, consuming significantly less amount of static power. The conventional 6T and 8T SRAM architectures have been implemented using this novel H-DGTFET operating at low supply voltage of 0.3 V. The performance of the 6T and 8T SRAM cells have been analyzed in terms of hold, read & write SNMs and total average power consumption. The read SNM for 6T and 8T SRAM cells have been found to be 54 mV and 69 mV respectively; hold and write SNM for 6T are 90 mV and 103 mV respectively. Total average power consumption for 6T and 8T SRAM cells are 2.13 μW and 2.68 μW respectively in one cycle consisting of two reads and one write “0”/write “1” operations.