Performance analysis of 65 nm CMOS LNA using SSL technique for 5G cellular front-end receivers

Abstract

This paper presents a performance analysis of a wideband low noise amplifier (LNA) that utilizes a 65 nm CMOS Samsung mm-wave process. The proposed CMOS LNA designed with new built-in techniques will overcome the challenges faced by device parasitic and electromagnetic (EM) losses. A suspended substrate line (SSL) is characterized and analyzed with its dual-band operation and achieves excellent EM compatibility. The traditional EM losses in bulk active and passive components have been incurred using built-in techniques to provide better linearity of LNA. The proposed mm-wave LNA enables it’s each family component to avoid leakage of EM waves and its interconnected parasitic losses in layout. An SSL based parallel-series network is optimized to achieve a wide bandwidth of 26 GHz to 34 GHz. The full design of LNA achieves the highest peak gain of 25 dB by using proper 50 Ω matching constraints over the wideband response of 27.8 GHz to 32.5 GHz. The fabricated chip of LNA is given a supply voltage of 1.2 V, and the calculated chip area is 0.35*0.22 mm2. The simulation and measurement results demonstrate the minimum noise figure of 2.5 dB and achieve the highest stability factor in the desired band of operation. The LNA also measured linearity with a 1 dB compression point where input power of −19dBm has obtained at 30.5 GHz.