Abstract
AbstractMultilevel rectifiers (MLRs) have been gaining popularity in a variety of applications due to their many advantages over two‐level rectifiers such as reduced voltage stress on power switches, much better harmonic profile of the input waveform, reduced dv/dt stress, possibility of fault tolerant operation, and so on. The use of higher number of semiconductor devices which are relatively more prone to faults plays a crucial role in determining the reliability of the system. In recent literature the performance analysis of the MLR in terms of cost, efficiency, reliability, and voltage stress has been majorly ignored. A five‐level rectifier topology with self‐voltage balancing capability has been implemented in this paper. The implemented topology has the capability to maintain the unity power factor (UPF) in all operating conditions. The in‐depth performance analysis in terms of reliability, efficiency and cost has been carried out to establish the suitability of the implemented topology for real‐time applications. In addition, the effect of various parameters on reliability has also been investigated. The MLR topology has been validated through experimentation. A qualitative and quantitative comparison of the proposed work with state‐of‐art has also been presented.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: International Journal of Circuit Theory and Applications
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
