Performance Analysis and Optimal Design of BATS Code: A Hardware Perspective

Abstract

Batched Sparse codes (BATS codes) are a class of <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">linear network coding</b> schemes that increase network throughput by converting a multi-hop problem into an end-to-end problem through network coding. It plays a crucial role in future wireless communication, where packet loss is inevitable. This is an enduring problem in many applications, including vehicular networks. While the theory of BATS codes has been developed over the past decade, little research has been done on its hardware implementation, which is important for practical adoption. This paper provides a systematic way to analyze the performance of a BATS hardware accelerator when the code varies. A roofline model which provides an upper bound of the performance considering both computational and input/output constraints is developed. Next, we build a model connecting the BATS code design space with the hardware execution time, which can be used to determine an optimal code. Finally, we propose and test a flexible and scalable BATS code design paradigm for hardware accelerators with numerical results. The same framework could easily be extended to other linear codes and different computing systems.