Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices

Abstract

This work presents a transistor sizing tool to optimize performance taking into account area and power consumption in MOSFET and FinFET devices. The sizing tool is based on Geometric Programming (GP). This tool is modeled to deal with the discrete behavior of FinFET transistor sizing due to the width quantization of these devices. ISCAS'85 benchmark circuits were mapped to a typical standard cell library in 45nm bulk CMOS technology. The size characteristics of this library were adapted to build a predictive 14nm FinFET cell library. Considering transistor sizes generally used in a standard cell library, our transistor sizing improves the delay of MOSFET circuits in 52.5%, on average, keeping almost the same area and power than the sizing provided by the standard-cell library. Good results are achieved considering two simple techniques to adjust continuous to discrete sizing for FinFET circuits: rounding and truncation. These simple sizing strategies produce FinFET circuits 77% faster, on average, keeping the same area and power. Further, results show that the performance can be significantly improved if is considered a Performance Dedicated Cell Library with more cells sizes than the adopted in traditional cell libraries.