Abstract
This letter designs the performance enhancement guaranteed cache (PEG-C) for hard real-time systems. The PEG-C uses two counters to monitor the number of hits and misses at runtime to improve the average-case performance, while guaranteeing the worst-case execution time (WCET). Our experiments indicate that with a few preloaded instructions, a PEG instruction cache can achieve the same average-case performance as a regular instruction cache while ensuring performance enhancement even in the worst case.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
