PEARL: Performance analysis of ultra low power reversible logic circuits against DPA attacks

Abstract

Reversible logic is one of the most vital issues at present time and it has major role in cryptographic applications. Security of cryptographic devices like smart cards has come under threat from powerful side channel attacks like Differential Power Analysis (DPA) attacks. DPA uses power dissipation information leaked from the secure IC to retrieve the secret key stored in it. To address this problem, we have proposed a novel gate which introduces the reversible two-input logical operations with minimum power dissipation for each logical operation. Therefore, the proposed gate mitigates the DPA attacks since the proposed logic dissipates very low power compared to DPA ressistant logic styles such as Sense Amplifier Based Logic (SABL), Wave Dynamic Differential Logic (WDDL), Masked Dual-rail Precharge logic style (MDPL) and Delay based Dual-rail Precharge Logic (DDPL) which is thereby useful in the design of secure integrated circuits. The experimental results have been carried out using Cadence© design tools in 180nm technology. The obtained simulation results of the proposed gate are appreciably better in terms of power dissipation as well as security when compared to the designs in literature.