Peak Power Reduction Through Dynamic Partitioning of Scan Chains

Abstract

Serial shift operations in scan-based testing impose elevated levels of power dissipation, endangering the reliability of the chip being tested. Scan chain partitioning techniques are quite effective in reducing test power, as the rippling in the clock network, in the scan chains, and in the combination logic is reduced altogether. Partitioning approaches implemented in a static manner may fail to reduce peak power down to the desired level, however, depending on the transition distribution of the problematic pattern in the statically constructed scan chain partitions. In this paper, we propose a dynamic partitioning approach capable of adapting to the transition distribution of any test pattern, and thus of delivering near-perfect peak power reductions. We formulate the scan chain partitioning problem via integer linear programming (ILP) and also propose an efficient greedy heuristic. The proposed partitioning hardware allows for the partitioning reconfiguration on a per test pattern basis, enabling the dynamic partitioning. Significant peak power reductions are thus attained cost-effectively.