Abstract
In order to achieve a low thermal resistance path directly beneath high power dissipating transistors, a thermal via and printed circuit board (PCB) optimization study was performed. The thermal resistance normal to the PCB surface served as the primary reference output, while the calculation parameterization was varied to minimize this thermal resistance. A fractional factorial designed experiment (DOE) was developed using MINITABtrade statistical software for the following thermal via and PCB factors, evaluated at two levels: via diameter, pitch, and barrel thickness as well as PCB top Cu pad area and number of metalized layers. The results for each DOE treatment combination were simulated as a parametric run using a finite volume computational fluid dynamics (CFD) software tool - Icepakreg. Steady-state thermal resistance values, from a power source on top of PCB to the bottom of board, were determined. This demonstrates a methodology of coupling statistical DOE with thermal CFD to efficiently optimize the thermal performance during the early design process
Published Version
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