Pattern recognition algorithms on FPGAs and CPUs for the ATLAS LVL2 trigger

Abstract

Recent studies of the level-two (LVL2) trigger of the ATLAS detector show that it will be possible to run the trigger algorithms at high luminosity with a reasonable number of general-purpose processors, using a sequential selection scheme and guidance from the Region-of-Interest (RoI) provided by the LVL1 trigger. The computing power requirements for B-physics, which is studied at low luminosity, are much greater than those at high luminosity as there is no LVL1-guidance for the track finding algorithms. Instead, track finding is performed for the entire Inner Detector volume. Currently, 2500 commodity CPUs would be required to supply the necessary computing power for the B-physics trigger. We describe a system of only 200 computing nodes which would be capable of performing the B-physics triggering. Each of these nodes is made up of a commodity PC and a FPGA co-processor board. Each node processes an entire event. The different tasks are allocated to the appropriate hardware device (CPU or FPGA). Track reconstruction requires a variety of different steps, some of which are suited to parallel processing, whereas others require sequential execution. For some tasks, floating-point arithmetic is needed. The flexibility of the PC/FPGA combination meets these varied requirements well.