Pattern Freezing Process Free Litho–Litho–Etch Double Patterning

Abstract

Double patterning technology based on existing ArF immersion lithography is considered as the most viable option for complementary metal oxide semiconductor (CMOS) node of 32 nm and below. Most of double patterning approaches previously described requires intermediate processing step such as hard mask etching, spacer material deposition, and resist pattern freezing. The requirement of these additional steps is now leading way to requests for throughput reduction and low cost for production for double patterning technology applications. In this paper, litho–litho–etch (LLE) double patterning without any intermediate processing steps is investigated to achieve narrow pitch resist imaging. The LLE options examined in this work are combinations of positive tone-negative tone and positive tone-positive tone photoresist double patterning process. These are the alternative processes in pattern freezing process free LLE double patterning. The goals of this work are to determine witch of these approaches is the most viable for future application and to confirm the patterning potential for 32 nm and below half pitch resist imaging.