Path-delay-fault testability properties of multiplexor-based networks

Abstract

We investigate the path-delay-fault testability properties of multilevel networks derived based on free (unordered) Binary Decision Diagrams (BDDs). We show, using a theoretical result of [18], that if the multilevel network derived from a BDD by replacing the vertices of the BDD by multiplexors is found to be fully single-stuck-at fault testable, then it is guaranteed to be completely robustly path-delay-fault testable. For networks derived from BDDs that are not initially single stuck-at fault testable, we give an efficient single stuck-at fault redundancy removal procedure tailored to such networks. We show that at the end of this procedure only a single form of robust path-delay-fault untestability, due to the blockage of paths by other paths, can exist in the single stuck-at fault irredundant network. This form of untestability can be easily removed to result in a fully robustly path-delay-fault testable network. Stuck-at fault redundancy removal in a general multilevel network may result in complicated forms of path untestabilities which require significantly more complex strategies for path-delay-fault testability enhancement. We present experimental results using the above synthesis procedures on examples of significant size such as a data encryption chip, a key schedule generator, and small μprocessors. Unlike previous synthesis techniques that ensure complete robust path-delay-fault test ability, this procedure can be used to synthesize fully testable circuits directly from non-flattenable, logic-level implementations, provided that Binary Decision Diagrams of reasonable size can be constructed for these logic implementations.