Patch-Based Adversarial Training for Error-Aware Circuit Annotation of Delayered IC Images

Abstract

Circuit annotation is one of the most important tasks in the analysis of integrated circuit images for hardware assurance. Recently, deep learning methods have been adopted for circuit annotation due to their promising accuracy. However, the pixel-wise optimization metrics in deep learning methods are insufficient to ensure a good spatial contiguity in the segmentation results. This could result in circuit connection errors that are detrimental to the subsequent circuit analysis. In this paper, a patch-based adversarial training framework is proposed to mitigate such circuit connection errors. Our proposed method consists of a encoder-decoder segmentation network and a patch-based discriminator to provide adversarial supervision for the segmentation network. The adversarial training aligns the distributions of the segmentation results with the ground truth in patches, which we hypothesize to be more effective for mitigating circuit connection errors. In our experiments, we have achieved a 17.4% reduction in circuit connection errors as compared to the second best reported technique. We investigated the explainability of our proposed method through a heat map analysis, and demonstrate that our patch-based discriminator has a higher feature response in regions that are likely to contain circuit connection errors.