Abstract

Generalized multiprotocol label switching (GMPLS) with wavelength division multiplexing (WDM) technology is a very promising protocol technology for future optical networks. GMPLS technology interconnects new and legacy networks by automating connection provisioning and traffic engineering. The present electrical interconnects for the system on chip (SoC) are unable to satisfy the multiple design requirements of bandwidth, data rate and latency. In this paper, for the first time we have proposed a micro resonator based GMPLS router for optical network on chip (ONoC). The evolution of such a router node on integrated circuit technology will cause the system design to move towards a communication-based architecture. The concept of an integrated GMPLS optical interconnect will be a potential technological solution, alleviating some of the more pressing issues involved in exchanging data between cores in SoC architectures. The investigation for ONoC was carried out at the physical level, where the system performance on the basis of crosstalk, blocking probability, offered traffic load and packet error rate was analyzed.

Highlights

  • Future data transmission networks will consist of elements such as; routers, switches, Dense Wavelength Division Multiplexing (DWDM) systems, Add-Drop Multiplexers (ADMs), photonic cross-connects (PXCs), optical cross-connects (OXCs) etc., that will use Generalized Multi-Protocol Label Switching (GMPLS) to dynamically provision resources and to provide network survivability using protection and restoration techniques

  • In this paper we studied the relationship between the network size in terms of number of OXC stages, crosstalk, optical SNR, and Bit error rate (BER) and found the possible number of routing stages in an optical network on chip (ONoC) with acceptable OSNR

  • A novel micro resonator based GMPLS router structure for ONoC design is investigated on the basis of crosstalk, blocking probability and packet error rate

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Summary

Introduction

Future data transmission networks will consist of elements such as; routers, switches, Dense Wavelength Division Multiplexing (DWDM) systems, Add-Drop Multiplexers (ADMs), photonic cross-connects (PXCs), optical cross-connects (OXCs) etc., that will use Generalized Multi-Protocol Label Switching (GMPLS) to dynamically provision resources and to provide network survivability using protection and restoration techniques. With the use of a GMPLS control plane at the physical level, the asynchronous transfer mode and Internet protocol layers are merged, as shown in Fig., to provide more transparency and dynamic re-configurability. It supports packet switching along with time, space and wavelength switching. We have proposed the micro-resonator based GMPLS router for optical network on chip (ONoC), with which the existing system on chip (SoC) will be able to give maximum throughput with minimum blocking probability. For the first time we have proposed the micro resonator based GMPLS router, crosstalk and blocking probability analysis for ONoC at the physical level.

Optical Network on Chip architecture
Analytical Modeling
Results and Discussions
Conclusion
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