Abstract
Serial scan approaches lead to a considerable reduction in the test generation cost for sequential circuits. However, they do present some drawbacks, such as area overhead I/O pin overhead and high test application time. A new full-scan approach is described named design, capable of substantially reducing the test application time. The paper focuses particularly on the case of single PASE-scan structures. An heuristic procedure is proposed to establish the configuration of the single PASE-scan structure and the placing of its memory elements. The experiments carried out with a set of ISCAS89 circuits show reductions in test length, with respect to the full single serial scan-path case, of up to 91% and 87%, depending on the compaction (low or normal) of the applied test set, and average reductions of 62% and 55%, respectively.
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