PaSE: A parallel speedup estimation framework for Network-on-Chip based multicore systems

Abstract

The massive integration of cores in multicore system has enabled chip designer to design systems while meeting the power-performance demands of the applications. However, full-system simulations traditionally used to evaluate the speedup of these systems are computationally expensive and time consuming. On the other hand, analytical speedup models such as Amdahl's law are powerful and fast ways to calculate the achievable speedup of these systems. However, Amdahl's Law disregards the communication among the cores that play a vital role in defining the achievable speedup with the multicore systems. To bridge this gap, in this work, we present PaSE a parallel speedup estimation framework for multicore systems that considers the latency of the Network-on-Chip (NoC). To accurately capture the latency of the NoC we also propose a queuing theory based analytical model. We conduct a case study for a matrix multiplication application and evaluate and analyze the speedup from our framework.