Partitioning VLSI floorplans by staircase channels for global routing

Abstract

This paper identifies a new problem of geometric partitioning of VLSI floorplans, called mincost staircase partitioning. We propose a framework for channel definition in global routing. In a VLSI floorplan, the isothetic rectangular circuit modules are placed on a 2-D floor with nets attached to each block. The objective of global routing is to determine the channels through which the terminals attached to different modules belonging to the same net are connected. Here we have mapped the global routing problem into a series of hierarchical staircase channel routing. To minimize the routing congestion, in each level of hierarchy we find a monotone staircase channel minimizing the number of distinct nets, having terminals on both sides of the channel. We give an O(n/spl times/k) time algorithm for the two-terminal net problem, where n and k are the number of blocks and distinct nets respectively. For multi-terminal nets the time complexity is O((n+k)/spl times/T), T being the total number of terminals on the floor.