Abstract
A key challenge in the synthesis and subsequent analysis of supervisory controllers is the impact of state-space explosion caused by concurrency. The main bottleneck is often the memory needed to store the composition of plant and requirement automata and the resulting supervisor. Partial-order reduction (POR) is a well-established technique that alleviates this issue in the field of model checking. It does so by exploiting redundancy in the model with respect to the properties of interest. For controller synthesis, the functional properties of interest are nonblockingness, controllability, and least-restrictiveness, but also performance properties, such as throughput and latency are of interest. We propose an on-the-fly POR on the input model that preserves both functional and performance properties in the synthesized supervisory controller. This improves the scalability of the synthesis (and any subsequent performance analysis). Synthesis experiments show the effectiveness of the POR on a set of realistic manufacturing system models.
Highlights
Supervisory controller synthesis [1] is a method to automatically synthesize a supervisor that restricts the behavior of a system, described by a plant, to a given requirement that describes the allowed behaviors of the plant
Standard synthesis first computes the composition of all plant and requirement automata, and subsequently prunes the state space to ensure properties like controllability and nonblockingness of the resulting supervisor [1], [2]
We presented a partial-order reduction (POR) technique for a network of automata specifying a plant and its requirements to obtain a smaller supervisor, while preserving controllability, nonblockingness, reduced least-restrictiveness, throughput, and latency
Summary
Supervisory controller synthesis [1] is a method to automatically synthesize a supervisor that restricts the behavior of a system, described by a plant, to a given requirement that describes the allowed behaviors of the plant. A (max,+) timing matrix expresses the relation between the availability times of the system resources and the release times of the resources after executing an activity Such a (max,+) timing model enables efficient performance analysis [15]. Given the supervisor and the timing matrices of the activities, a timed (max,+) state space can be computed that provides the necessary timing information to evaluate system throughput and latency. Our POR technique improves scalability of the supervisor synthesis It preserves both functional and performance properties, which in turn improves scalability of any subsequent performance analysis. Our POR technique can be used on conventional finite-state automata with events, by assuming activities do not claim or release resources and are assigned the empty 0 × 0 (max,+) timing matrix (implying that they are timeless).
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