PARNEU: general-purpose partial tree computer

Abstract

PARNEU is a parallel co-processor system for a PC designed for artificial neural networks, and other computationally intensive applications. PARNEU topology includes a bus, ring and reconfigurable partial tree, which are motivated due to analysis of several algorithms. The architecture provides very versatile mapping possibilities and allows modular hardware implementation. An important feature is practical expandability without signal and clock skew problems. Analog Devices ADSP-21062 digital signal processors and Xilinx field programmable gate arrays are used for cost-effective and reliable implementation. PARNEU programming is convenient due to C-primitives, which hide the complex communication and allow high level language software development. In addition, PARNEU can be remotely used over Internet due to a TCP/IP server. The hardware performance metrics as well as the application performance for Multilayer Perceptron (MLP), Self-Organizing Map (SOM) and Sparse Distributed Memory (SDM) neural networks are given. Performance improvements of the order of 20–40 times are achieved compared to our previous neurocomputer implementation called TUTNC.