Abstract
In this paper, an all-optical parity checker and parity generator circuit is proposed in which SOA-MZI configuration is used to implement the XOR logic gate. This performance monitoring logic device is simulated at ultra high speed i.e. 120GHz. Two logic circuits are proposed for parity generator, in one design inverter used to generate parity bit is implemented by the same additional XOR gate as inverter while in 2nd design inverter is implemented using XGM in SOA and thus number of SOA in 2nd design is reduced. ER ratio achieved in 1st case is 9.28 with maximum Q factor 73.39 and minimum BER 0 while in 2nd design it is 9.35 with maximum Q factor 8.41 and minimum BER 1.93e−17. ER ratio achieved in parity checker circuit is 32.54 with maximum Q factor 77.76 and minimum BER 0.
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