Pareto Optimal Characterization of a Microwave Transistor

Abstract

Herein, noise, gain and port mismatchings of a microwave small-signal transistor are expressed as all the set of acceptable Pareto optimal solutions and trade-off relations within the device operation ( $\text{V}_{\mathrm {DS}}$ , $\text{I}_{\mathrm {DS}}$ , $f$ ) domain without any need of expert knowledge of microwave device. In this multi-objective optimization problem, non-dominated sorting genetic algorithm (NSGA) -III is applied to an ultra-low noise amplifier (LNA) transistor NE3511S02 (HJ-FET) where the noise $\text{F}_{\mathrm {req}}\ge \text {F}_{\mathrm {min}}$ and output mismatching $\text{V}_{\mathrm {outreq}} \ge 1$ are preferred as the reference points, while the input mismatching $\text{V}_{\mathrm {inopt}} \ge 1 $ and gain $\text{G}_{\mathrm {Tmax}}$ are optimized with respect to source $\text{Z}_{\mathrm {S}}$ and load $\text{Z}_{\mathrm {L}}$ within the unconditionally stable working area. Thus, diverse set of the Pareto optimal (the required noise $\text{F}_{\mathrm {req}}$ , the optimum input $\text{V}_{\mathrm {inopt}}$ , the required output $\text{V}_{\mathrm {outreq}}$ , the maximum transducer gain $\text{G}_{\mathrm {Tmax}}$ ) quadruples are resulted from a fast search of the solution space. Furthermore, the optimum bias condition ( $\text{V}_{\mathrm {DS}}$ , $\text{I}_{\mathrm {DS}}$ ) and sensitivities of the terminations to fabrication tolerances are also determined using the cost analysis in the operation domain for the required $\text{P}_{\mathrm {max}}$ , $\text{I}_{\mathrm {DSmax}}$ and performance quadruple. Finally, this work is expected to enable a designer to provide the feasible design target space (FDTS) consisting of all trade-off relations among all the transistor’s performance ingredients to be used in the challenging LNA designs.