Parasitics Triggered Stress Analysis in Active Clamp Synchronous Forward converter

Abstract

Low switching losses, high frequency operation enabling high power density, efficiency, and reduced voltage stress are the bench-marking parameters for active clamp forward converters. Synchronous rectifiers further aid the cause of loss reduction by lowering the secondary side losses. However, these inherently come with a value of high parasitic capacitances $(C_{p})$, which play an important role in the behaviour of these topologies. Their interaction with resonant inductor $(L_{r})$ in the primary side leads to oscillations in the resonant inductor current and primary switch voltages - an effect, which gets increasingly pronounced with higher parasitic capacitance values. It also results in high switch voltage stress, thereby undermining the benefits of switch voltage clamping. This paper analyzes the effects and discusses the change in topological modes with both low and high parasitic capacitance. This paper also analyzes the changes in the switch voltage stress with the addition of L<inf>r</inf> and discusses the design criterion to arrive at its upper limit based on the maximum allowable voltage stress across the main switch.