Parasitic Parameter Effects on the dv/dt-induced Low-side MOSFET False Turn-on in Synchronous Buck Converters

Abstract

This paper investigates impact of parasitic parameters on the dv/dt-induced low-side MOSFET false turn-on in synchronous Buck converters. Because of the MOSFET resistance and packaging inductance, induced gate-to-source voltage of the low-side MOSFET during the high-side MOSFET turn-on transition cannot be readily measured. To analyze parasitic parameter effects on the MOSFET false triggering, this paper utilizes a newly proposed analytical model to perform the task. The study covers a much larger group of parasitic parameters compared with the existing study using a simple analytical model. As a result of the quantitative investigation, new insight into the problem is uncovered, and effective design strategies can be developed accordingly to prevent such a problem from taking place in practical designs.