Parasitic Extraction with Metal Fill Effects Consideration in IC Design Flow to Improve Design Cycle

Abstract

In integrated circuit (IC) fabrication, chemical-mechanical planarization (CMP) is a process used for achieving a uniformed surface on the wafer through a combination of chemical and mechanical effects. While CMP is the preferred planarization technique, the surface damage created is a major concern as it leads to performance degradation and yield loss. The severity of surface damage is dependent on the uniformity of metal density of the wafer. To overcome this problem, metal fill insertion is introduced to ensure uniformed metal density and minimal topological variation after the CMP process. However, metal fill insertion will contribute to parasitic effects changes on on-chip interconnect layers. Thus, it is crucial to be able to predict and estimate parasitic effects contributed by both neighboring nets and metal fill early in the design cycle to prevent over-designing and under-designing. This paper introduces a design flow which takes into account parasitic effects of metal fill early in the design cycle through metal fill emulation to provide a form of early fill effect modeling so that design engineers to not over-design or under-design. Experiments performed shows that parasitic extraction with emulated metal fill achieved accuracy with the largest difference of 21.2% compared to extraction performed on a test-design with router-based filler.