Parasitic Back-Gate Effect in 3-D Fully Depleted Silicon on Insulator Integrated Circuits

Abstract

3-D integrated circuits (ICs) promise to deliver faster, more compact circuitry with lower power consumption than equivalent planar ICs. However, 3-D integration introduces unique noise sources not present in planar ICs. In this paper, we identify how interconnect on a backside metal layer acts as a back gate of transistors on the adjacent tiers in 3-D fully depleted silicon on insulator technology. The resulting shift in threshold voltage is determined by process and backside interconnect geometries. We develop a framework to evaluate the impact of process parameters. Our results show that coupling due to backside metal results in 5X more electrostatic noise coupling than nearby through-oxide vias. The results also show that the change in threshold voltage of an NFET device increases with thicker front oxide, thinner buried oxide, thinner silicon film, and increased backside metal voltage. Additionally, we simulate the adverse effects of back-gate coupling on circuit performance using a representative analog test circuit, an analog amplifier. We show that the back-gate voltage can change the output of an inverting amplifier by as much as the output swing of the amplifier (0.058 V) under normal operation.