Parametric study of flip-chip packaging for an MEMS device with diaphragm

Abstract

In present study, a backside-etched silicon chip with a polysilicon diaphragm flip-chip attached on a printed wiring board (PWB) and globally bumped on a FR4 substrate was investigated based on finite element analysis (FEA) for determining three key parameters of flip chip chip size packaging (FC-CSP), namely, the size of solder bump, the thickness of PWB substrate, with/without U8437-3 underfill. In order to improve the reliability and the yield of MEMS packaging, the thermal cycle of environmental test ranging from −40° to 125° was utilized for determination of the influence of key parameters on the thermal-induced stresses and the deflection in the diaphragm as well as the warp of PWB substrate. In addition, the thermal stress occurred at the interface between solder bump and silicon chip was also analyzed to understand the failure mechanism of solder bump. According to the simulation results, we concluded three phenomena as follow: (1) As the thickness of substrate increased, the thermally-induced stress in the diaphragm also increased, but the deflections of diaphragm and substrate decreased instead. (2) As the size of solder bump increased, both of stress and deflection in the diaphragm decreased, however, the warp of substrate was insensitive to the size of solder bump. (3) If the underfill material encapsulated the solder bump between chip and substrate, the induced stress occurred at the interface between solder joint and chip was decreased, however, the stress in the diaphragm was increased instead. On the other hand, the deflection was smaller in the diaphragm but larger in the substrate as the underfill existed in the model. In general, the parametric study can provide the basis for the flip chip package of MEMS device with diaphragm, such as MEMS microphone, MEMS pressure sensor, etc.